The present invention relates to a memory circuit, and more particularly to a memory circuit which permits serial or parallel data output.
A memory element suitable for image processing is described in an article by Ishimoto et al, entitled "A 256K Dual-Port Memory", 1985 IEEE International Solid-State Circuits Conference Digest of Papers, pages 38-39. The disclosed dual-port memory comprises a random port constructed by a conventional randomly readable and writable 64K-words.times.4-bits memory cell array, and a serial port which can be consecutively read out 4 bits in parallel by a clock operation from a 256-words.times.4-bits data latch circuit. A prior art device which uses such a dual-port memory such as, for example, an image memory of a video display is explained. The serial port of the dual-port memory can be consecutively read out 4 bits in parallel at a cycle time of 40 nanoseconds. Thus, a 10 ns serial data is produced by converting the 4-bit parallel to serial data by a shift register arranged externally of the memory so that the data is fitted to a dot rate necessary to a high resolution video display. A dot rate necessary to a conventional 640.times.400-dots display is approximately 45 ns. When a cycle time of the serial port output of the dual-port memory is set to 40 ns, it appears that the serial port output can be used as it is. However, in this case, the following problem is encountered.
FIG. 9 shows a configuration of 4 frames of image memory for a 16-color display in a 640.times.400-dots display. Since the number of pixels is equal to 640.times.400=256,000 dots, one 64K-words .times.4-bits dual-port memory is required for one frame of memory, and the 4 frames of image memory comprise four memories. In FIG. 9, data times RD0, -----, RD15 at the random ports of dual-port memories 11, 12, 13 and 14 are connected to a 16-bit width data bus 10 of a CPU (Central Processing Unit, not shown). The data lines RD0, -----, RD15 are connected to four random ports, of which only one random port 111 is shown with the internal configuration of dual port memory 11. Data output lines SD0, -----, SD15 from serial ports 112 etc. are connected to input terminals of shift registers 15, 16, 17 and 18, four lines per shift register, and output lines SF1, -----, SF4 therefrom are connected to input terminals of a color palette 19. The color palette 19 decodes signals applied from the output lines SF1, ----, SF4 to select one of sixteen colors to produce color signals R (red), G (green) and B (blue).
A problem encountered here is that, in the conventional display, the shift register 15 is required externally of the dual-port memory 11 to produce the signal SF1, and a total of four shift registers are required. Thus, the number of components increases.
On the other hand, it is possible to configure the memory such that the shift register 15 is accommodated within the dual-port memory 11. In this case, however, the memory cannot be applied to the high resolution display.